IC Verification

Produtos.

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IC Verification

Ferramentas para Desenvolvimento de Circuitos Integrados contemplando as etapas de Desenho, Simulação, Layout, Verificação e Manufatura de CI Analógico, Digital, Mixed-Signal, RF (Radiofrequência) e MEMS (Micro ElectroMechanical Systems).

AnalogFastSPICE™ (AFS)

The world’s fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits.

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Questa ADMS™

zQuesta ADMS™ gives designers a comprehensive environment for verifying complex analog/mixed-signal (AMS) System-on-Chip (SoC) designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo® for general purpose analog simulations, Questa® for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RF for modulated steady state simulation.

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Questa ADMS RF

Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems. Complete simulation of RF system-on-chip (SoC) designs becomes a reality when you combination the RF capabilities of Eldo RF with the mixed signal capabilities of Questa ADMS. Built upon these solid foundations, the Questa ADMS RF solution allows effective simulation of communication systems containing tightly linked RF and baseband functions—analog and digital.

 

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Questa® Clock-Domain Crossing (CDC)

Questa CDC Solutions identify errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another.

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Questa® Formal Verification

The Questa® Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states. This exhaustive analysis ensures that critical control blocks work correctly in all cases and locates design errors that may be missed in simulation.

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Questa® inFact

Questa® inFact is the industry’s most advanced testbench automation solution. It targets as much functionality as traditional constrained random testing, but achieves coverage goals 10X to 100X faster.

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Questa® Power Aware Simulator

The Questa® Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation, but starting much earlier in the design process.

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Questa® Advanced Simulator

The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF. The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Platform; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

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Questa® Verification Management

When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And not just to the verification plan, but also to the specifications and the design, both of which change over time. There are three dimensions to any IC design project: the process, the tools and the data. Questa® offers a comprehensive approach to the problem with its verification management option that handles all within a scalable and modular solution.

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Questa® Reset Check

Reset signal distribution is becoming more complex than ever, creating second-order effects that aren’t modeled by RTL simulation. Sharing a common language front end with the Questa Simulator, and leveraging the formal-based, high-performance Questa CDC algorithms under-the-hood, Questa Reset Check is the perfect tool to identify and fix unexpected, chip killing reset signaling issues.

 

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Questa® Codelink

Codelink is the industry's leading software driven hardware verification solution. It makes every verification engineer an instant "CPU expert" by providing 100% accurate processor views for system level testing.

 

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Visualizer Debug Environment

High performance debug environment for digital design and verification. Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs..

 

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Certus™ Silicon Debug

Certus enables debugging system- and chip-level issues by enabling efficient instrumentation of 1,000’s of signals with the ability to capture very deep traces. Easy software-driven run-time configurability eliminates costly re-instrumentation spins. Certusintegratesintoexistingimplementationflows.

 

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ADiT

ADiT is the tool of choice to address the challenges associated with simulating today’s complex analog and mixed signal circuit designs. ADiT is a fast-SPICE simulation tool that delivers the ability to obtain accurate and reliable simulation results 10X – 100X faster than traditional SPICE tools. ADiTis integrated into the Questa ADMS mixed-signal simulation solution and supports both Eldo and HSPICE netlist formats.

 

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Eldo Classic

Foundry Certified SPICE Accurate Circuit Simulation. When accuracy matters designers choose Eldo Classic, Mentor’s “golden” SPICE accurate circuit simulator, designed to address the complex needs of analog and mixed-signal designers.

 

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Eldo Premier

Eldo Premier, Mentor’s new Faster-SPICE product, addresses the primary concerns of analog and mixed-signal designers, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy.

 

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Eldo RF

Transistor-level simulator for RF IC designs. The analysis and measurement capabilities of Eldo RF help designers verify complex RF IC designs more quickly and accurately. From simple compression or intermodulation analysis to complex digital modulation, Eldo RF powerful algorithms make genuine verification a reality.

 

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ICanalyst™

ICanalyst™ is an advanced verification cockpit that enables designers to easily leverage the full complement of Mentor Graphics analog mixed-signal solutions for design verification and analog cell characterization: Questa® ADMS for mixed-signal, Eldo® (Classic and Premier) for SPICE, and ADiT™ for Fast-SPICE applications. ICanalyst accomplishes this through an optimized design flow purposed for automating repetitive tasks.

 

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Kronos Analyzer

Cell Library Analysis & Validation. Kronos Analyzer is a comprehensive library analysis and validation solution.

 

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Kronos Characterizer Plus

Cell Library Characterization. Kronos Characterizer Plus is a high-throughput, general purpose cell library characterization tool for standard cells, memory, IO Pad, and custom macros.

 

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Calibre InRoute

Calibre® InRoute™ enables designers to achieve signoff manufacturing closure during physical design by providing complete integration between the Calibre platform, the industry leader for manufacturing signoff, and Mentor’s award-winning Olympus-SoC place and route system.

 

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Calibre xACT

Calibre® xACT™ delivers high performance parasitic extraction for digital, custom, analog and RF designs. With its integrated fast 3D field solver and highly parallel architecture, CalibrexACT provides attofarad accuracy with the performance needed for multi-million instance designs.

 

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Calibre xACT 3D

Calibre® xACT 3D features a 3D field solver modeling engine built on advanced software algorithms to accurately calculate parasitic effects at the transistor level. Using CalibrexACT 3D on a multi-CPU platform makes extraction turnaround time competitive with the rule-based tools, shortening design cycle times.

 

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Calibre nmLVS

Calibre® nmLVS, the market-leading layout vs. schematic physical verification tool, is tightly linked with both CalibrenmDRC and CalibrexRC™ to deliver production-proven device extraction for both physical verification and parasitic extraction.

 

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Calibre® PatternMatching

Calibre® Pattern Matching replaces lengthy and multi-operational text-based design rules with an automated visual geometry capture and compare process that significantly reduces rule deck size and improves congruence between the original intent of the design specification and its implementation.

 

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Calibre® Auto-Waivers™

Calibre® Auto-Waivers™ provides automated recognition and removal of waived design rule violations during DRC. Calibre Auto-Waivers not only eliminates costly time and effort from the verification process, but also ensures accurate processing of all waiver information on every DRC run. Reducing design verification time while simultaneously improving the quality of results can provide the market edge you need to stay ahead of your competition.

 

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Calibre® Interactive™

Calibre® Interactive™ is the invocation GUI for Calibre DRC™, LVS and xRC™ tools for physical verification and parasitic extraction. It’s easily accessed from the menu bar within popular layout design environments.

 

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Calibre RVE

Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre RVE provides the debugging technology you need for fast, accurate error resolution.

 

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Calibre® DESIGNrev™

For engineers integrating and assembling complete chips, the process of going from first pass integration to successful tape-out can be lengthy and difficult. With design size and complexity increasing, traditional layout editors lack the capability to quickly and efficiently visualize, revise and stream-out layout data. Performing simple tasks on large full-chip GDSII and OASIS® files, and preparing the design for the mask manufacturing process (chip finishing), often can take hours, delaying tape-out. Calibre® DESIGNrev™ speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.

 

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Calibre® RealTime

Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.

 

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Calibre 3DSTACK

Calibre 3DSTACK extends Calibre die-level signoff verification to enable complete signoff verification of a wide variety of 2.5D and 3D stacked die assemblies. With Calibre 3DSTACK, designers can perform signoff DRC and LVS checking of complete multi-die systems at any process node without breaking current tool flows or requiring new data formats, significantly reducing time to tapeout. Because 3DSTACK is enabled using standard Calibre DRC, Calibre LVS and CalibreDESIGNrev license features, no new licenses or tools are required.

 

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Calibre® PERC™

Calibre® PERC™, Mentor Graphics' newest reliability verification solution is designed to address your advanced circuit verification needs for electrostatic discharge (ESD), electrical overstress (EOS), signals crossing multiple power domains, advanced ERC and other reliability concerns.

 

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Calibre® xRC™

Calibre® xRC™ is a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. Calibre xRCisabletoextractinterconnectparasiticshierarchically.

 

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Calibre® xL

Calibre® xL offers designers full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Results of CalibrexL extraction highly correlate with field solvers and have silicon-tested accuracy.

 

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