IC Design

Produtos.

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IC Design

Ferramentas para Desenvolvimento de Circuitos Integrados contemplando as etapas de Desenho, Simulação, Layout, Verificação e Manufatura de CI Analógico, Digital, Mixed-Signal, RF (Radiofrequência) e MEMS (Micro Electro Mechanical Systems).

Pyxis Schematic

Pyxis Schematic, part of Mentor's new Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.

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Pyxis Implement

Pyxis Implement, part of Mentor's new Pyxis Custom IC Design Platform, provides a highly productive environment for correct by construction layout entry and editing.

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Pyxis Layout

Pyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing.

 

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Design Kits

The design kits contain customizable, easily expandable building blocks for schematic capture, simulation, physical layout, and verification, which allow you to create a complete, integrated IC design environment that’s tailored to the foundry process technology for your design.

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Olympus-SoC™

The Olympus-SoC™ Netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the leading-edge process nodes. It is a complete physical design implementation tool for the complex multi-patterning and FinFET requirements of advanced process technologies.

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Oasys-RTL™

The Oasys-RTL physical RTL synthesis solution addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities. Oasys-RTL provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time.

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Tanner S-Edit

Tanner S-Edit schematic capture increases your design productivity while handling the most complex IC designs. This powerful environment supports fast, 64-bit rendering and cross-probing between schematic, layout, and LVS reporting at net and device levels.

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Tanner T-Spice

The Tanner T-Spice simulator, part of the Tanner Tool Suite, integrates easily with other design tools in the flow and is compatible with industry-leading standards. It improves simulation accuracy with advanced modeling, multi-threading support, device-state plotting, real-time waveform viewing, and analysis, and a command wizard for simple SPICE syntax creation.

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Tanner Waveform Viewer

Tanner Waveform Viewer (formerly known as W:Edit) provides an intuitive multiple-window, multiple-chart interface for easy viewing of waveforms and data in highly configurable formats.

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Tanner L-Edit IC

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable. Create layouts that match the schematic the first time, maximizing efficiency and reducing the CAD manager’s support burden. Get up and running easily with platform independence and flexible licensing.

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Tanner Place & Route

Integrated, flexible digital place & route tool that speeds development of analog/mixed-signal designs. Tanner Place & Route is optimized for the needs of 'big' analog / 'little' digital mixed-signal designs on typical analog process nodes. It is a critical part of the Tanner AMS end-to-end flow for analog/mixed-signal designs. Highly flexible, Tanner Place & Route delivers unparalleled flexibility during every phase of the flow.

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Tanner Verify DRC and LVS

Tanner Verify DRC and LVS is a comprehensive solution for analog/mixed-signal IC Design Rule Checking (DRC) and netlist extraction. Its 64-bit engine enables fast, simple debugging through DRC and netlist extraction, and uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs.

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Tanner Parasitic Extraction

Tanner Parasitic Extraction (formerly HiPer PX Parasitic Extraction) extracts circuit parasitics so you can get the design right the first time with accurate interconnect modeling. It includes fast 2D extraction, accurate 3D modeling and the ability to quickly extract simulation-ready SPICE netlists from layout, including devices and interconnect parasitics.

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Tessent Boundary Scan

Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing IC engineering development effort and improving time-to-market.

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Tessent FastScan

Tessent® FastScan™ simplifies the process of generating high-coverage compact test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available. Comprehensive at-speed test is critical to ensure high-quality testing. TessentFastScan’s at-speed tests include transition, multiple detect transition, timing-aware, and critical path.

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Tessent IJTAG

To manage the complex requirements of testing a heterogeneous set of embedded IP, the industry developed IEEE 1687 (IJTAG). It standardizes a language for describing the IP interface and how IPs are connected to each other. It also introduces a language that defines how patterns that operate or test the IP are to be described. IEEE 1687 draws a clear line between what must be covered by the standard and what is better left to the ingenuity of the tool developers.

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Tessent LogicBIST

Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market while maximizing test quality.

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Tessent Scan

Tessent® Scan™ inserts scan test structure into a netlist, delivering design that is completely ready for scan testing and pattern compression. Tessent Scan generates and adds the most effective scan architecture for your design, ensuring high-quality test with automatic test pattern generation (ATPG). It performs scan flop replacement and stitching, analyzes your circuit for possible test limitations, does test-related design rule checks (DRCs), and automatically corrects errors.

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Tessent ScanPro

Tessent® ScanPro provides all the functionality of Tessent Scan plus advanced scan DFT features that maximize the performance of scan-based test solutions. TessentScanPro includes a unique test point generation and integration process that directly targets ATPG pattern volume reduction. This EDT Test Point technology typically improves test compression levels by 2x to 4x and is effective at reducing patterns generated for all types of fault models.

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Tessent TestKompress

Tessent® TestKompress® delivers the highest quality deterministic scan test with the lowest manufacturing test cost. The solution uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment.

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Tessent® MemoryBIST

Tessent® MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level..

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Tessent® PLLTest

Tessent® PLLTest provides complete, parametric, embedded test for PLLs, DLLs, and clock signals. It can measure jitter, phase delay, duty cycle, frequency ratio, lock time, and lock range, all in less than 100 ms, including test set-up and on-chip comparison to test limits via the IEEE 1149.1 TAP interface.

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Tessent® SerdesTest

Tessent® SerdesTest provides complete, parametric, embedded test for multi-Gb/s SerDes. It measures waveshape, many types of jitter, and various jitter tolerance parameters, all in less than 200 ms, including test set-up and on-chip comparison to test limits via an IEEE 1149.1 TAP interface.

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Tessent® Diagnosis

Tessent® YieldInsight® statistically analyzes diagnosis data to identify and separate systematic yield limiters before any failure analysis is done.

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Tessent® YieldInsight®

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable. Create layouts that match the schematic the first time, maximizing efficiency and reducing the CAD manager’s support burden. Get up and running easily with platform independence and flexible licensing.

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Tessent® SiliconInsight®

The Tessent® SiliconInsight® solution provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent BIST or Tessent IJTAG test structures.

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